The Intel 8259A Programmable Interrupt Controller | Search for a title, author or keyword | ||||||||
The Intel 8259A Programmable Interrupt Controller The Programmable Interrupt Controller ( PIC ) accepts requests from the peripheral equipment, determines which of the incoming requests is of the highest importance ( priority ), ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination. Each peripheral device or structure usually has a special program or routine that is associated with its specific functional or operational requirements; this is referred to as a service routine. The PIC, after issuing an Interrupt to the CPU, must somehow input information into the CPU that can point the Program Counter to the service routine associated with the requesting device. The 8259A is a device specifically designed for use in real time, interrupt driven microcomputer systems. It manages eight levels or requests and has built-in features for expandability to other 8259A's ( up to 64 levels ). The 8259A can be easily interconnected in a system of one master with up to eight slaves to handle up to 64 priority levels. The interrupts at the IR input lines ( IR0 ... IR7 ) are handled by two registers in cascade, the Interrupt Request Register ( IRR ) and the In-Service ( ISR ). The IRR is used to store all the interrupt levels which are requesting service; and the ISR is used to store all the interrupt levels which are being serviced.
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